1. Technical Field
The embodiments described here relate to a semiconductor memory apparatus, and, in particular, to a circuit for generating an output enable signal in a semiconductor memory apparatus, which supports stable data output operations.
2. Related Art
A conventional, semiconductor memory apparatus can include a plurality of data output drivers (DQ) and a plurality of data output strobe signal drivers (DQS), for performing data output operations. The data output driver performs the operation of receiving rising and falling data output clocks transmitted from a data output clock generator and then synchronizing data with the respective clocks. The data output clock generator generates the rising data output clock using an output enable signal and a rising clock having a high level at a rising edge time of a delay locked loop (DLL) clock output from a DLL circuit. The data output clock generator generates the falling data output clock using an output enable signal and a falling clock having a high level at a falling edge time of the (DLL) clock output from the DLL circuit. The semiconductor memory device includes a circuit for generating an output enable signal, thereby generating an output enable signal from a command signal, a burst length signal and a clock.